An LDMOS transistor which is used in a high-voltage power device has advantages of fast switching speed, high input impedance, low power consumption, and compatibility with a CMOS process, and is widely used in various power devices including a display driving IC, a power converter, a motor controller, and a power supply for a vehicle. In the case of a power device, since on-resistance and breakdown voltage are important factors which significantly affects the device performance, various techniques have been suggested so as to increase the breakdown voltage while maintaining on-resistance Rsp.
For example, a structure has been suggested in which an internal field ring made of a dopant of a type opposite to a drift region is formed below the gate end portion in the drift region of the LDMOS transistor.
On the other hand, the breakdown voltage characteristic of the semiconductor device is closely related to the radius of curvature of a source region or a drain region. In particular, the radius of curvature of the relatively small source region is one of the main factors which may cause a decrease in the breakdown voltage of the device, due to an electric field concentration phenomenon occurring in a junction area having a small radius of curvature.
FIG. 1 is a layout view of a power semiconductor device of the related art, for example, an LDMOS transistor. FIG. 2 is a sectional view taken along the line of FIG. 1. In FIGS. 1 and 2, the same reference numerals represent the same regions or layers.
As illustrated in FIGS. 1 and 2, the LDMOS transistor of the related art includes a source 10, a drain 20, a source-side protrusion 10′, a drain-side protrusion 20′, a gate 30, and an N drift region 40. The drain 20 is separated from the source 10 at a predetermined interval.
The source 10 includes a source electrode on the surface of a p-type semiconductor substrate 1 and is a highly doped n+ type source region formed in the semiconductor substrate 1 below the source electrode.
The drain 20 includes a drain electrode on the surface of the semiconductor substrate 1 and an N drift region 40 formed in the semiconductor substrate 1 below the drain electrode. The N drift region 40 is an n-well region formed by an n-type impurity ion implantation process.
As illustrated in FIG. 2, the drain 20 is an n+ type drain region formed inside the N drift region 40. A p-type top region 25 is formed inside the N drift region 40.
The gate 30 is formed so as to be insulated from an underlying channel region by a gate insulating film 50, and the source electrode, the drain electrode, and a gate electrode are insulated from each other by an insulating interlayer.
The LDMOS transistor also includes a field oxide film 42 having a LOCOS structure.
The semiconductor having the LDMOS transistor of the related art analyzes the ratio of the number of electric charges in the layout corresponding to the N drift region 40 and the P-type top region 25 to obtain the optimum conditions of the breakdown voltage and the on-resistance.
In the case of an LDMOS which is used in a high-voltage application, from the viewpoint of design layout, there is a phenomenon that the charge balance is lost depending on the boundary condition. That is, in a source finger structure in which a round is formed on the basis of the source 10 or a drain finger structure in which a round is formed on the basis of the drain 20, there is a phenomenon that the optimum breakdown voltage characteristic decreases. In particular, in the case of an n-type LDMOS, it is more difficult to ensure the breakdown voltage characteristic, having a limit to ensure the breakdown voltage due to the corner effect. In general, in order to correct the phenomenon that the breakdown voltage of the n-type LDMOS is limited, a method is used in which the n-type LDMOS of the corner region is not taken into consideration, or a method is used in which the n-type LDMOS characteristic is taken into consideration but limitedly used.
According to these methods, there is a phenomenon that the device characteristic per cross-sectional area of the LDMOS is not ensured. Accordingly, there is demand for a method capable of ensuring the optimum LDMOS characteristic per given size.